Digital System Design and Synthesis

Introduction to hardware description languages, automated synthesis, and advanced digital design principles.

offering recorded3 credits
Recorded instructors · Fall 2026 Julie Hsiao

Summary

1 / 7

Historical reviews of Anthony Gregerson, Mikko Lipasti, Younghyun Kim: The semester project requires significant effort and early planning. Workload varies widely, with some noting overwhelming weekly assignments or challenging midterm coding exams.

Grade history

average GPA
letter grades
A
AB
B
BC
C
D
F

All recorded terms · compare terms & instructors

Prerequisites

Course map

E C E/​COMP SCI 352, graduate/professional standing, or member of Engineering Guest Students

    • COMPSCI/ECE 352
    • graduate/professional standing
    • member of Engineering Guest Students
    take one
ECE 551 used by

“Used by” includes alternatives; linked courses may have other requirements. This is a best-effort interpretation; check the catalog requirements above.

Prerequisite text tree
  • Any of
    • COMPSCI/ECE 352
    • graduate/professional standing
    • member of Engineering Guest Students

Professors

Fall 2026

Recent recorded grades — Fall 2025: 3.25 GPA, 50.0% A/AB (n=26 letter grades); Spring 2026: 3.31 GPA, 60.3% A/AB (n=78 letter grades).

Historical instructors & teaching patterns

Historical reviews of Eric Hoffman: Eric Hoffman is a knowledgeable instructor who explains Verilog and synthesis clearly, bringing industry experience to a skills-heavy class. Reviewers note his videos are organized and he is helpful, making him a strong choice for learning digital design.

ANTHONY GREGERSON is recorded teaching in Fall 2010, Spring 2011. Recorded history may be incomplete and does not establish a future schedule.

ERIC HOFFMAN is recorded teaching in Fall 2008, Fall 2009, Spring 2012, Fall 2012, Spring 2013, Fall 2014, Spring 2015, Fall 2015, Spring 2016, Fall 2017, Fall 2018, Spring 2019, Fall 2019, Spring 2020, Fall 2020, Fall 2021, Spring 2022, Fall 2022, Spring 2023, Fall 2023, Spring 2024, Fall 2024, Fall 2025. Recorded history may be incomplete and does not establish a future schedule.

JULIE HSIAO is recorded teaching in Fall 2025, Spring 2026. Recorded history may be incomplete and does not establish a future schedule.

KATHERINE MORROW is recorded teaching in Spring 2009, Fall 2010, Spring 2011. Recorded history may be incomplete and does not establish a future schedule.

MICHAEL MORROW is recorded teaching in Fall 2007, Fall 2011. Recorded history may be incomplete and does not establish a future schedule.

MIKKO LIPASTI is recorded teaching in Fall 2016. Recorded history may be incomplete and does not establish a future schedule.

YOUNGHYUN KIM is recorded teaching in Fall 2016, Spring 2017, Spring 2018. Recorded history may be incomplete and does not establish a future schedule.

Recorded history may be incomplete and does not establish a future schedule.

Calendar & sections

Fall 2026

Schedule loads here as you scroll.

SectionModeEnrolled / capacityWaitlist
LEC 001Classroom Instruction78 / 850
DIS 301Classroom Instruction24 / 450

Times are Central. Select a meeting for details; export includes recorded dates for the selected sections. Enrollment reflects scan time.

Meeting source records

Student experience

the class

Historical reviews describe the course as skills- and project-heavy, with Eric Hoffman praised for clear explanations of Verilog and synthesis. Other instructors receive mixed feedback, ranging from helpful to unorganized.

Recent recorded grades — Spring 2025: 2.96 GPA, 39.2% A/AB (n=79 letter grades); Fall 2025: 3.31 GPA, 57.5% A/AB (n=106 letter grades); Spring 2026: 3.31 GPA, 60.3% A/AB (n=78 letter grades).

difficulty & workload

Historical reviews of Anthony Gregerson, Mikko Lipasti, Younghyun Kim: The semester project requires significant effort and early planning. Workload varies widely, with some noting overwhelming weekly assignments or challenging midterm coding exams.

Historical reviews of Eric Hoffman, Parmesh Ramanathan: Students find Eric Hoffman's organized videos and helpfulness useful for learning digital design. Conversely, others report frustration with Parmesh Ramanathan's unhelpful lectures and unclear grading rubrics.

Topics

  • Verilog and VHDL description languages
  • Synthesis from hardware description languages
  • Timing-oriented synthesis
  • IC layout and timing-oriented design
  • Design for reuse

Skills

  • Use of hardware description languages (Verilog, VHDL) and automated synthesis.
  • Timing-oriented synthesis techniques.
  • Understanding the relation of IC layout to timing.
  • Design for reuse principles.

Grades

Historical instructor

Fall 2026 · Projected

Before grades are released

average GPA

Approximate 80% prediction interval

About this estimate

The course’s semester-average GPA, not an individual student’s grade. The center uses 5 same-season terms, weighted toward recent results.

The range uses the finite-sample 80th-percentile rank of absolute errors from earlier same-season forecasts. Each forecast uses only records from earlier terms. At least four forecasts are required; bounds are rounded outward and limited to 0–4. This is an empirical estimate: changing instructors or grading policies can reduce its coverage.

8 earlier forecasts · 0.03 GPA average error.

Grades over time

Through Fall 2026

More grade details Grade mix, volume & source data

Where this course fits relative to

Latest available grades · Spring 2026 · all course levels

GPA

Higher than % of other courses in this group.

Course GPAs · red marks this course’s range

letter grades

More recorded grades than % of other courses in this group.

Typical course in this group: letter grades.

About this comparison

1283 courses over the same term, each with at least 30 recorded letter grades. Cross-listed courses count once. GPA is not a measure of difficulty or teaching quality. The typical course is the median by recorded grade count; tied values are not counted as lower. Grade counts describe course scale, not unique students or typical section size.

Descriptions compare GPA with this group’s average: at least 0.20 higher or lower; otherwise close to average. Section size uses median recorded enrollment: small up to 30, mid-sized 31–99, large 100+. Lectures and discussion/lab sections are described separately.

Sources & history

UW–Madison

Catalog & offerings

Descriptions, prerequisites, and recorded course offerings.

Catalog observation history

Observations at scan time; dates do not imply when a catalog change took effect.

Selected offering source records
ECE 551 · Fall 2026

Digital System Design and Synthesis

Recorded 2026-09-07
Raw records
[
  {
    "run_id": "20260907T155543-ce3781c4",
    "semester": "1272",
    "observed_at": "2026-09-07 15:55:43.033547+00:00",
    "offering_id": "1272:320:021682",
    "course_id": "ECE 551",
    "course_uid": "course_42330966f01392dae105b4e1",
    "term_id": "1272",
    "source_course_id": "021682",
    "source_subject_id": "320",
    "title": "Digital System Design and Synthesis",
    "credits_min": 3,
    "credits_max": 3,
    "typically_offered": "Fall, Spring"
  }
]
Rate My Professors

Student reviews

Original comments behind the course and instructor summaries.

Read original reviews
Madgrades

Grade history

Recorded grade distributions by term, section, and instructor.

Explore recorded grades
Model outputs & technical records
nvidia/Qwen3.6-35B-A3B-NVFP4
LLM outputs across runs
Full model traces

Recorded model configuration, reasoning, and tool conversations.

Model & dataset provenance
{
  "model": "nvidia/Qwen3.6-35B-A3B-NVFP4",
  "model_revision": "1355db6a052410cfd62085d94b58866fd0f2c3c5",
  "task_version": "14",
  "output_id": "b2b14bac57ad9c864e9fb8dea512cadc4642e3a76ea4681342333c1bdb6d09e1",
  "requirements_status": "valid",
  "dataset_revision": "e243353dcb7d79b7247ced91d69443ef4c2a6349",
  "observed_at": "2026-09-07 15:55:43.033547+00:00"
}