[{"run_id":"20260906T231458-5fdd2fff","semester":"1272","observed_at":"2026-09-06 23:14:58.172943+00:00","record_version_id":"4dffe155238fbb670a623470eaf118457799ce375182d205f2bbc747e3b0cad7","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"20260907T155543-ce3781c4","semester":"1272","observed_at":"2026-09-07 15:55:43.033547+00:00","record_version_id":"4dffe155238fbb670a623470eaf118457799ce375182d205f2bbc747e3b0cad7","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-03b0bbb9723907cf3d1b41cf0bb34837dc398e42","semester":"1262","observed_at":"2025-04-16 05:20:33.104844+00:00","record_version_id":"43a87c590661c298161b46288f97d65853530933a947f7cdaf585e3ae631fed1","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0837245627eb714ae6bb0375f7abe8f41042011f","semester":"1262","observed_at":"2025-04-16 05:20:33.104844+00:00","record_version_id":"43a87c590661c298161b46288f97d65853530933a947f7cdaf585e3ae631fed1","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-08c92e359bbbc110b0778b7e0b15d6f40000e6b1","semester":"1262","observed_at":"2025-08-21 07:05:14.730696+00:00","record_version_id":"f3f05b72a31e9c0a03199b943a0d2007eefdf0fc09728e05965e1a87ece4629e","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0944d76440dc778fbb89626058c10451009ce9c6","semester":"1262","observed_at":"2025-05-21 03:36:18.194118+00:00","record_version_id":"f7720cf37292b8e6702e5fd26b74d7b21bb49075c1887f5bf48a2bb75a102c9f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0a7f4bce29c816ef4d3d71b4eb8a2a3e15e33cc1","semester":"1262","observed_at":"2025-06-18 20:04:02.695444+00:00","record_version_id":"07406741956ad009bfd9c01b235d43ee7dc44d6b3da072726269080b804d933c","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0ab917f827a7de22ebdc1087114d377a31c4687b","semester":"1262","observed_at":"2025-05-22 02:11:02.531191+00:00","record_version_id":"b51cc2351bcc4df46be5e75fa457f6f713e420389e8e3fe05c5b5614ccc285c1","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0c40ecab4b6db9333d1f18aef816e3ee659e300c","semester":"1262","observed_at":"2025-05-25 18:02:34.797617+00:00","record_version_id":"437be0e41cae7f50993dd9c5bb110c469a5602dc49e0b3cfaa6e893d87db0999","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-0cb4d29a588ec7f11c7e00b7cf5dc3a0d23d0349","semester":"1266","observed_at":"2026-01-22 01:00:26.555427+00:00","record_version_id":"f983fb72dc9ab9d0d2fcc34f188c02b812da83914c5545cfb7519cb5650a2e58","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-11c30ec39e91498cbfcf3a923c53a4b03e387280","semester":"1262","observed_at":"2025-07-20 04:58:26.847117+00:00","record_version_id":"0301d26ceecc07782496655deb12f1674f64bce21d05f7413b22a9f3e983cbce","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-13cd500edf2587e9a3428f326253738fbea965ea","semester":"1264","observed_at":"2025-12-14 04:50:04.653658+00:00","record_version_id":"b1daa6c33ecbe2fb93eda23d6bacb611c3da7bbc873a6a88aa8e80e496621c59","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-1da08b2de39f05e6bc877c189fc2fd6eeda563f5","semester":"1262","observed_at":"2025-07-01 00:03:56.707251+00:00","record_version_id":"c7dcbce6efc75d401ba670eac883e7c93e2b930a64790de5ede30c4ecd2357ae","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-2031af47efe133b0e7877f433286ff07385afc41","semester":"1262","observed_at":"2025-07-02 20:16:45.749584+00:00","record_version_id":"c7a94be0f028e279a0b56b87a9eefff10e37cbfbee324e77d422f51a6ed46ba8","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-238eba6f32fbc30407f616dd0628ff02a2a824dd","semester":"1262","observed_at":"2025-08-17 05:15:07.788352+00:00","record_version_id":"72680eb8596a7f9c868181ca0ab3049a9f6f1b122e8f1e92d24c10b3c8ed2533","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-25f0ff56bc4d80f8a8afa1a0bcce8dae6fddb5e5","semester":"1262","observed_at":"2025-05-25 17:20:25.942090+00:00","record_version_id":"297778c7369db094167d6f08abce710fa3f0706ba593120dbe6d0bfe1b7c9fb2","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-2923f91826ce253b7aeefa9f75b4a39fe4c80ff0","semester":"1262","observed_at":"2025-08-10 05:10:25.938416+00:00","record_version_id":"5372e8188fa25b24f76f23eeebd3ac37182935f80ce9f7fde43c448a7fcdbc13","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-2a05214a4023e0157fa6f7d188c85308f714176c","semester":"1262","observed_at":"2025-09-07 04:56:38.255315+00:00","record_version_id":"5975f899fe2c9a4313cae068641edb63454f0f50259b21929ef78789eb7e029b","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-2b1b8e39131de92b94620b25c5bbb25690efed4c","semester":"1262","observed_at":"2025-06-01 07:54:53.913454+00:00","record_version_id":"399cbdbd6f6563321e85104b5b1115b9d622fe1aebd04719ec02d049626fa8d1","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-33a1225644e5a5855d60f66e65413946e72fedf4","semester":"1262","observed_at":"2025-06-22 01:52:05.152650+00:00","record_version_id":"158513a45834475d9144968bb7d8e8fc7d4b1674cacb1a2b01f9266161e8b387","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-3b89c83dbf5208e13756184de1f2b2d0c09af35f","semester":"1262","observed_at":"2025-06-30 06:40:10.235522+00:00","record_version_id":"2a319330e53e43e06c04c7ed9610f9a98868aae557b14d1345de07146c4177e0","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-3c3eebf7f35c39364b445a2fa5a112ce28dbb4a1","semester":"1262","observed_at":"2025-06-01 17:03:59.062985+00:00","record_version_id":"3d54957d9516a4390a9b75864f230d792589c110e73d9bda33d80a5409bb33c6","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-3fa4dd71391f1c9cf4ab2216680bbc428689f92d","semester":"1262","observed_at":"2025-05-25 01:15:58.180530+00:00","record_version_id":"f2d5c5b810e66d9b38aec109d06b9d3c6986aaf0abb01c6f91cfefb91cc5e969","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-4040aa216da722a34483f68fc1e129ea571ae08d","semester":"1262","observed_at":"2025-06-01 07:27:39.695506+00:00","record_version_id":"cbee1c2b2a4a2eeeb138b1b3f91a8ea3902238f4dc348e46cd90e52348a276ef","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-454d53cd690294459f8ad0793cc3ed562060e56c","semester":"1262","observed_at":"2025-05-25 01:34:00.536004+00:00","record_version_id":"853369f3e3f3f85b62a557165a16117250edae99b113e9c802933f24fb4d02ed","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-486f091e051fdb4ccdb80ee7b4fb0a5814510324","semester":"1264","observed_at":"2025-11-16 05:32:31.273726+00:00","record_version_id":"cdc58bbff9ae18e9870850142e379262b6608247728e2968a72cfe0d1a19d68d","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-50393cfc5fd5598d4f4731ef1919f2ff53af07d9","semester":"1262","observed_at":"2025-06-30 06:05:57.438846+00:00","record_version_id":"a0898dfe3c22ddf77b4d29ea9c720ba51b808fc983bb76a6e6c7b93639dca4f9","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-50f6947786b208c800db8bbd0cec84a8f0f187d2","semester":"1262","observed_at":"2025-06-02 03:49:42.915428+00:00","record_version_id":"3e4e51b69b0d6b7c9fb7cd76197e718dd540a39f2e4e8925deb4c9d687ff3249","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-51d86ed4082dced3803c295419b0ec8440942016","semester":"1264","observed_at":"2025-11-12 04:50:41.141307+00:00","record_version_id":"dbc6abe594931c7a619069fd2165d927487e8b786779c94720295a1997efdc92","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-53101bd1c10db0d00d094e4c9154d4c244ff23d9","semester":"1262","observed_at":"2025-10-05 04:58:05.366968+00:00","record_version_id":"a33761129713e8b01931969ee24f17fbd73d24f6940e87134a95f8f50a50d5f4","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-58751151c564e11c5cb8aedd3a2d3527c22f73eb","semester":"1262","observed_at":"2025-06-01 06:59:01.536576+00:00","record_version_id":"29495e48f8d4788af716d6561616d7e85ddb5a6280fe311059d6fa288ef468e2","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-5c4c8d3701a333ba4ddadef7d0b5dde8440fcdf0","semester":"1262","observed_at":"2025-06-01 01:57:51.256704+00:00","record_version_id":"3d414d492ea2a73c00240f72106b44dc354f5c0c6a50a00fb12f9921075aee28","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-5d20d9f81651d3c83fcaa2fd10870ce6e5d5a685","semester":"1262","observed_at":"2025-05-21 16:48:48.484741+00:00","record_version_id":"14d3f62626880825580649072f75fda2c3aca276040e57c028aad1c75c333d96","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-5feaebf2ab37051c86ad360cc0fa0d7e0e2ea295","semester":"1262","observed_at":"2025-05-24 15:58:23.378859+00:00","record_version_id":"a546e53b479b8154e2dc76acd823f3569a8d8f5410602cecf03583f58638e4e0","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-60949965544fce098cc006354e201149005fb77b","semester":"1264","observed_at":"2025-10-26 05:07:14.077864+00:00","record_version_id":"1e12ad0597fc49f0d2d03ae0d3334d5ae6412720a38b70166629b1177b19421f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-639225ac3addf8522f1d30cb4fe26054ea7f8c49","semester":"1262","observed_at":"2025-06-01 08:14:42.497608+00:00","record_version_id":"bd8d48d12c2fe1a72143d5f5e47bcdc4d2a40040fdf96fcf1468705b9c2b96b7","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-64093b17b3a9c67a41aa33eb37adb53ec38df714","semester":"1262","observed_at":"2025-05-22 02:11:02.531191+00:00","record_version_id":"b0053bd0550824b9c51479a73c01a065006a94ccacfb807a666e380bfa6b3650","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-6885b56099f55e08aa0205546369fb0381d50e13","semester":"1262","observed_at":"2025-07-13 04:59:22.367394+00:00","record_version_id":"ec3cb11b917843ab11574176400b512e75887f5bd200c79f3e6754c69fd8affe","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-69d4b2b16e8268f75b6390b3a0e2ce8bf73999da","semester":"1262","observed_at":"2025-06-30 03:21:29.925498+00:00","record_version_id":"b653372fa468719af8cab7e0bc5934f076eaa08e7c8b0322ed5ce277a44803bf","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-6b29c3e0673b2f9a736d2363db5409e03d5b3ed4","semester":"1264","observed_at":"2025-12-03 12:33:41.418072+00:00","record_version_id":"00e0fef87c6ebc194a9a1b8a4151caad4301e4a24b550fa9bacbbefa87b77074","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-73259984748de484976ef2ad56ad7ab3d4cb4518","semester":"1262","observed_at":"2025-06-26 08:27:56.461216+00:00","record_version_id":"a5493c8dbd90ce825dc791310064f2ebe86e2ecac971c14488994f3fbfbeb0b0","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-741602fbc6252c232a0b9e6bc1a9ae3101625f5a","semester":"1262","observed_at":"2025-06-30 22:49:32.522034+00:00","record_version_id":"c1c53b8f197d1513e0ca69caa286fb4dc194cd17a9ecee27b89999933fdabfe9","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-7774f45558276ec29bf626e58fffb4a27bdbb2a9","semester":"1264","observed_at":"2025-11-01 11:49:36.359151+00:00","record_version_id":"e6b85b7ee5c294cefad78bc34888f4ae183422ee8c1986f3e6c6a6950b72baba","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-7ab7c5e783fc8ebef8b8ee8cea019ee37a72ce74","semester":"1262","observed_at":"2025-09-28 04:58:07.340658+00:00","record_version_id":"cb2fc9945588c1cea05eb792268ae04c1d1a060d396908d5ca00f33ca79fa952","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-7b2f22d83ea05055ab90dcb77dc802382cccc6f7","semester":"1262","observed_at":"2025-05-21 17:56:46.096741+00:00","record_version_id":"80e3cb297a623fd2eb4ccfd43c40d563190a54db7c0e2628b3223c6055869ec6","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-7ca1175502be18eb51f7b016818a884a43fd4ebb","semester":"1262","observed_at":"2025-07-29 06:28:23.644795+00:00","record_version_id":"a023fc1b0fb4020723d2e526f5634a25dcbaf1d5836b55aafdd950833f93174f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-7d8cee5e42602ad9ba5dc0322085af2fa0dffaac","semester":"1262","observed_at":"2025-05-22 01:15:19.291664+00:00","record_version_id":"e25893e0e863932fd98e0fd99a663b696be6c6ea50336d8e8b2bbbb51e73f628","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-81a0d6a7f668c98c59bd05fa988aa079c5ad1f68","semester":"1262","observed_at":"2025-05-31 07:49:50.419452+00:00","record_version_id":"5caa7b8395ac5cd4076901544d547249a2924222a872467fd36e314015e608e2","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-82f31c08c746a214872494cde6ecaeb9330441b4","semester":"1262","observed_at":"2025-06-17 21:26:08.547156+00:00","record_version_id":"26b753ac47b535cd2fab928af0fcb0eb91e74f00553948173464a33635a7e21c","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-84c248343c5a99ab42c5616c594812a5e3e31cbb","semester":"1262","observed_at":"2025-07-04 06:00:07.487827+00:00","record_version_id":"8b4d25ed252cba266c8dffe6639a983ca9a78b63b41f4b709e2307814d7072c6","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-86334e7275e315853287e8580c35456c68df800b","semester":"1262","observed_at":"2025-05-22 06:53:03.336354+00:00","record_version_id":"67e75cbdb93c18d80d0cd638ab6dee0ea4ea5767b101577e645685aeca843d05","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-8686dc1664f93a6c05f50321410961b39b12f91b","semester":"1262","observed_at":"2025-05-28 10:17:41.595894+00:00","record_version_id":"315c8be6b53ec92193ff0fcd565d5016999d544207e5900d88bc3e94702481d6","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-86d941366886c9a14a2581c04e20d0bdd25e1b02","semester":"1262","observed_at":"2025-08-31 04:54:14.656039+00:00","record_version_id":"ebf048dac64252aadf7a21da176c99af48ce4d8ff18d33f955c5ea60f27dcc54","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-8ba1d2e6cfbb1525b4f9f769ec164fb6ad0f237a","semester":"1262","observed_at":"2025-06-02 05:22:45.010398+00:00","record_version_id":"f3dbf357c6aee0704d2f11ec7650500adeb34e07fddc672009ed9361103ab0da","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-90e5aa456689a3b222016c05c319bbcd0bddd453","semester":"1262","observed_at":"2025-05-25 02:00:10.037905+00:00","record_version_id":"1e98b185f3861cdff3201e0e7df125873033ce9bc4a4b5577c51863a77b0b043","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-92d960aa7e4cd6e4c9ac8b2e232092904038e9e4","semester":"1262","observed_at":"2025-06-08 01:50:46.451351+00:00","record_version_id":"a07a70bc49e4115f5473c3c2f03f43c21ca57072f65e6008e396eede5924aedf","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-94002ae588a8f71eca6d64105f2e603e8587293b","semester":"1262","observed_at":"2025-05-21 09:01:16.021508+00:00","record_version_id":"8afc0a10e5a71b7e467673c407fd808bae52bffe849ee71d10411039e689df13","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-9dd575e013c5c6e000ab3ad2d1288cc1dd9c96dc","semester":"1264","observed_at":"2025-12-21 04:47:46.589081+00:00","record_version_id":"2c35f1c9ad1676266c025132181f3b13214c3e6dad22d82cfb81eb2eac514c6c","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-a1ea26ed78cbd6e94bc3221e50a6ed9b6bf43871","semester":"1262","observed_at":"2025-05-25 09:16:55.180581+00:00","record_version_id":"a6016372a2d9efb3eff9344c8c7f6b959423033178c4c97ad05f63a62a913d06","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-a76a3505853d5ea9c13bb98472b87361d469e2ee","semester":"1262","observed_at":"2025-05-28 18:03:41.793846+00:00","record_version_id":"affac7010c9e41b209e136d49c630c06232815169e4450c2f9322a0bac07a23f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-b285d591f6acf3aa1910e02edc297664db86eb8c","semester":"1262","observed_at":"2025-06-10 22:48:22.460295+00:00","record_version_id":"fbb4a3aebbb2eef2d1264ff82fe6d461873611e247c2e9ee273ef22fb8385c9c","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-b79af756e4f00ba98231feb859ed8e98239eb811","semester":"1262","observed_at":"2025-05-22 02:47:56.931581+00:00","record_version_id":"032f40295a4a197411bc102e77aa5a1ae559d2129cf483425ec85888d9c6891f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-b89e05b94730c6471439082d9279c0a834a4aeec","semester":"1262","observed_at":"2025-08-26 20:25:42.325239+00:00","record_version_id":"50125cea4f629135c91cfed18b4a03c5f799e89a9182c6a51731eb4ed761644a","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-b9279a12d1f2688df9e556183c94d41a89e431dc","semester":"1262","observed_at":"2025-07-06 01:49:47.203835+00:00","record_version_id":"4677b84d6a994ddadec7165d40498aa5359a9261880e7862fe3a5651c7856231","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-bbdc905e96cc681a5e9a8b02c795b682206e36d1","semester":"1262","observed_at":"2025-06-25 08:02:45.445730+00:00","record_version_id":"2e7268f4b883ccd45481131b4f80161f910ad352b0964fd749117b3f9398a991","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-bde225b5243a13d81827aa173e39c78a652b54a0","semester":"1262","observed_at":"2025-05-23 07:22:33.219345+00:00","record_version_id":"a58d324d55ef362cd7bf942dc4e1029c94796649922caef7b7bf469d7b24b6e9","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-c1fac4cbfde737f4f4ac02cdf15e6f5a9b5b676d","semester":"1262","observed_at":"2025-05-22 01:15:19.291664+00:00","record_version_id":"e25893e0e863932fd98e0fd99a663b696be6c6ea50336d8e8b2bbbb51e73f628","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-c6b62be45f8a13cba109ef2a7741b9cd9a6b8272","semester":"1262","observed_at":"2025-08-24 08:48:09.035112+00:00","record_version_id":"b7af3d125e8932830423f19fa65919a7f92b001382d904d6da2cf1b2aa12ef2b","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-cc83f62cb6db61f39320916d819ad48ce55cd96d","semester":"1262","observed_at":"2025-05-22 00:45:35.735230+00:00","record_version_id":"61ed21d5d5418e49f4eb0adbb3be9cd4651859534180be088d2f00bfe357bd7c","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-d33818a01b6b4c5e2902e704da6e5b713742d4dc","semester":"1262","observed_at":"2025-10-13 10:46:24.251475+00:00","record_version_id":"7c3719d1fdd6a462b237dc95fa03e05f2e9a690ce2ba0696e03f0c9e3d42bfcc","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-d3c17db9832d3064916046caf891dd23f10b1bb9","semester":"1262","observed_at":"2025-08-26 11:30:42.288639+00:00","record_version_id":"9305f0fa72c1bddd99de935f414ff77f9e782f9d801144c1f2277329670765ae","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-d4ee226dc44268e9b6767fb9f5f20343322f494b","semester":"1262","observed_at":"2025-06-15 01:52:23.911697+00:00","record_version_id":"e166d353259473d62429b237697ed271eae2b8f7c0caa127e79e0d0875da843f","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-d8f9fc7f136e2033556d9d65bbdbdf33425dbdc9","semester":"1262","observed_at":"2025-05-28 16:48:12.400438+00:00","record_version_id":"118f730ff729f32dffcd56133ecc04996a7bc9242a466be4c9c0afab2d490986","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-dbbc9739c616c3846b2e796e00a36fa41225f7d8","semester":"1262","observed_at":"2025-06-01 17:47:19.325144+00:00","record_version_id":"202549309f3723f6b3adaae0299d24f639dabfaa94b738b5d7b3bce1cc38eb81","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-dbe5f2d24b48c3177297a3d69c553cc9d1194bac","semester":"1262","observed_at":"2025-09-14 05:00:27.366070+00:00","record_version_id":"2aa226ae6fdca55d0c7e32e22ccfc75bc9e09d16d980d83e06359e846584edcb","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-dd357dc2758e9e282c30988a527ce37de92593b9","semester":"1264","observed_at":"2025-10-19 01:39:41.951404+00:00","record_version_id":"e9051a4dc4f32d9c317be4c6c8a9b96f45e53f1de4cd4b03546aa90365f2b025","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-de74de559e409a3fe668685e28043b888d2e6841","semester":"1262","observed_at":"2025-06-27 07:38:50.882897+00:00","record_version_id":"0407709e9e125837fa99559f707f8cadce99db903352c6d956e4dffc0c90eff1","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-deca7188cf536ade3203cd88b52a45e92a059617","semester":"1262","observed_at":"2025-06-27 00:37:46.087071+00:00","record_version_id":"347b9382b500020db31cb3c8400f9e36c06f831c18f8e1507275cbc6077e2959","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-df60fa9ac3931c5612b0fa641b7a6f5fbec86fab","semester":"1262","observed_at":"2025-05-24 06:36:37.554678+00:00","record_version_id":"69f72e10ab286b4d9cf256160fef267ba9c24ca5b78290577703e1b7094d7e50","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-e339da2d849aaf8bb4dceca07a84728af23cf755","semester":"1262","observed_at":"2025-07-23 08:49:22.748925+00:00","record_version_id":"bf634686812ec9844c6790e6e5ae249492130b8a4f2adf229644f5c5c649f132","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-e934b1784835f5d36ae9b7ef0992b11e72c39142","semester":"1262","observed_at":"2025-06-01 06:21:25.219533+00:00","record_version_id":"90557fccaac8c4f9e9e10962456acfc9ceb83967d00de608b32fc26159d997f2","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-ef471690c082448deebd2687eab84b0b78813c36","semester":"1262","observed_at":"2025-06-29 01:47:56.317645+00:00","record_version_id":"fd13160264aa7c188808aeec3e370e6e29ee51dc3cd7a6f429aea66bee6e8cdc","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-efc4e8e2cd7c3f68e059a308990c00c77c7611eb","semester":"1264","observed_at":"2025-10-16 05:48:13.935141+00:00","record_version_id":"3d98e413bbf5f66e280f82906ee03b73092ce971f0fa017d819666fc22cafebc","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"},{"run_id":"legacy-f18b7749725097d41f69c60779ff38cf073b93b3","semester":"1262","observed_at":"2025-05-21 19:52:03.259353+00:00","record_version_id":"d4ab0f40c94499678002690c5a83f726e1647246cc48ed3e985f80a85d4a3b63","course_id":"COMPSCI/ECE 552","course_uid":"course_45a9d9a05cba4d5b592ac7a3","catalog_version_id":"edad5db290468c4fbd0b709e4e0c5f1ea3ee6f5753099ffb84a6bff95f9c1ddc","course_number":552,"subjects":["COMPSCI","ECE"],"title":"INTRODUCTION TO COMPUTER ARCHITECTURE","description":"The design of computer systems and components. Processor design, instruction set design, and addressing; control structures and microprogramming; memory management, caches, and memory hierarchies; and interrupts and I/O structures.E C E 551or knowledge of Verilog is recommended.","requirements_text":"(E C E/​COMP SCI  352andE C E/​COMP SCI  354) or graduate/professional standing"}]